1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a complementary metal oxide semiconductor (CMOS) device with dual gates and a method of manufacturing the same.
2. Description of the Related Art
Metal Oxide Semiconductor (MOS) transistors can generally be classified into N-channel Metal Oxide Semiconductor (NMOS) transistors and P-channel Metal Oxide Semiconductor (PMOS) transistors depending on a channel type. A CMOS transistor includes all characteristics of NMOS and PMOS since a CMOS transistor consists of an NMOS transistor and a PMOS transistor in a singular semiconductor device.
Polysilicon has been traditionally used as a gate electrode material for MOS-based transistors. The polysilicon gate electrode is typically doped with either P+ or N+ to match the doped source/drain regions in CMOS technology. However, as the size of semiconductor device continues to decrease, polysilicon becomes less effective as a material to be used as a gate electrode.
The polysilicon gate is highly doped so as to be nearly as conductive as metal, while the solubility (or concentration) of dopants in the polysilicon gate is limited to around 5×1020 atoms/cm3. Since the solubility of dopants restricts the number of charge carriers in the polysilicon gate, a depletion layer is formed at the interface between the polysilicon gate and a gate dielectric layer when the gate is biased. The depletion region in the polysilicon gate acts as an additional capacitance in series with the gate dielectric capacitance. In other words, the depletion region increases the equivalent oxide thickness (EOT) of the transistor by at least 4 to 6 Å, thereby decreasing the driving current of the transistor.
Meanwhile, the efficacy of a silicon oxide film or a silicon oxynitride film conventionally used as the gate dielectric layer has reached its limit because of the rapid decrease in size of semiconductor devices, and difficulties in securing the reliability of the gate dielectric layer. For example, if the silicon oxide film becomes thinner than 20 Å, the gate leakage current is increased by quantum-mechanical direct tunneling through the silicon oxide film, and the power consumption increases. Accordingly, there are limitations to the amount of reduction in the thickness of the gate dielectric layer formed of silicon oxide or silicon oxynitride.
To overcome this problem, research with regard to the use of alternative gate dielectrics with dielectric constants (k) higher than silicon oxide or silicon oxynitride is being actively conducted. Dielectrics having dielectric constants (k) higher than silicon oxide or silicon oxynitride are referred to as high-k dielectrics. When the high-k dielectrics are used as the gate dielectric layer, the physical thickness of the gate dielectric layer can be large while the EOT can be scaled down for compatibility with the other reduced feature sizes, and the leakage current generated between the gate electrode and a channel region can be decreased.
However, in MOS transistors utilizing high-k gate dielectrics and polysilicon gate electrodes, defect states and numerous bulk traps, which are generated at the interface between a semiconductor substrate and a gate dielectric layer, capture electrons contributing conduction so that a Fermi level is pinned on a charge neutrality level or a central portion of an energy band located around the charge neutrality level, thereby largely increasing the threshold voltage (Vth) of the transistor.
The polysilicon gate depletion effect and the Fermi level pinning phenomenon occur more seriously in the case of PMOS transistors. Particularly, in the PMOS transistors, boron penetrates from the polysilicon gate electrode doped with p+through the gate dielectric layer to the channel region of the semiconductor substrate, thereby varying the flatband voltage (Vfb) and threshold voltage (Vth), and deteriorating the device reliability.
The above-described problems may be solved forming a gate electrode having a similar work function as the one of either P or N doped polysilicon. The N doped polysilicon has a work function of approximately 4.2 eV whereas the P doped polysilicon has a work function of approximately 5.1 eV. The difficulty is to choose a material which is suitable to both these work function values.
Another option is to form a gate electrode using two different materials with one that is similar to the work function of the N-doped polysilicon, and the other that is similar to the work function of the P-doped polysilicon.
FIG. 1 is a cross-sectional view illustrating a semiconductor device with dual gate electrodes according to a conventional method.
Referring to FIG. 1, a gate dielectric layer 12 including a high-k dielectric such as HfO2 is formed on a semiconductor substrate 10 having PMOS and NMOS transistor regions.
A metal containing material such as tantalum nitride (TaN), which has a work function suitable to a PMOS transistor, is deposited on the gate dielectric layer 12 to form a metal gate layer. Then, the metal gate layer is wet-etched to leave a portion of the metal gate layer only on the PMOS transistor region.
After depositing a doped polysilicon layer on the gate dielectric layer 12 and the remaining portion of the metal gate layer, the polysilicon layer and the remaining portion of the metal gate layer are patterned by a lithography process. As a result, a gate stack 25 including a metal gate 14 and a polysilicon gate 16a is formed on the PMOS transistor region, while a polysilicon gate 16b is formed on the NMOS transistor region.
Here, a reference numeral 18 indicates source/drain regions of PMOS transistor and a reference numeral 20 indicates source/drain regions of NMOS transistor.
In the conventional method described above, it is difficult to etch the metal gate layer. The unnecessary portion of the metal gate layer is removed by a wet etching process in order to prevent the underlying gate dielectric layer from being damaged. In case that the metal gate layer is etched using a photoresist layer as an etching mask, the photoresist layer cannot effectively serve as the etching mask because the photoresist layer is removed by a wet etchant.
In the case where the metal gate layer is etched using a hard mask layer of silicon oxide, the underlying gate dielectric layer is removed together during a wet etching process of removing the hard mask layer.
In the case where the metal gate layer is etched using a hard mask layer of polysilicon, it is unnecessary to remove the polysilicon hard mask layer, thereby simplifying the process. However, since the polysilicon hard mask layer needs to be formed thicker than 300 Å due to the limitation of the process uniformity, a difference in height between the NMOS transistor region and the PMOS transistor region becomes larger, and thus the etching process for gate patterning becomes difficult.